;
; mem_dec.pds
; $Id: mem_dec.pds 1.1 1999/02/23 14:27:21 frago Exp frago $
;
; PALASM Design Description
;
; Memory decode circuit for Z80180 production board
; Decodes CE for 4 128kB memories,
; first 256 bytes of ROM1 always at address 0.
;
; Schematic device: D6
;
; Address map
;   00000-000ff ROM1
;   00100-1ffff RAM1
;   20000-3ffff RAM2
;   40000-5ffff ROM1
;   60000-7ffff ROM2
;   80000-fffff EXT_MEM

;---------------------------------- Declaration Segment ------------
TITLE    MEM_DEC.PDS
PATTERN  A
REVISION 1.0
AUTHOR   F Gormarker
COMPANY
DATE     990222

CHIP  MEM_DEC  PAL16V8

;---------------------------------- PIN Declarations ---------------
PIN  1          A8                   COMBINATORIAL             ; INPUT
PIN  2          A9                   COMBINATORIAL             ; INPUT
PIN  3          A10                  COMBINATORIAL             ; INPUT
PIN  4          A11                  COMBINATORIAL             ; INPUT
PIN  5          A12                  COMBINATORIAL             ; INPUT
PIN  6          A13                  COMBINATORIAL             ; INPUT
PIN  7          A14                  COMBINATORIAL             ; INPUT
PIN  8          A15                  COMBINATORIAL             ; INPUT
PIN  9          A16                  COMBINATORIAL             ; INPUT
PIN  10         GND                                            ; INPUT
PIN  11         A17                  COMBINATORIAL             ; INPUT
PIN  12         PAGE0                COMBINATORIAL             ; OUTPUT
PIN  13         RAM2_CE              COMBINATORIAL             ; OUTPUT
PIN  14         RAM1_CE              COMBINATORIAL             ; OUTPUT
PIN  15         ROM2_CE              COMBINATORIAL             ; OUTPUT
PIN  16         ROM1_CE              COMBINATORIAL             ; OUTPUT
PIN  17         MREQ                 COMBINATORIAL             ; INPUT
PIN  18         A19                  COMBINATORIAL             ; INPUT
PIN  19         A18                  COMBINATORIAL             ; INPUT
PIN  20         VCC                                            ; INPUT


;----------------------------------- Boolean Equation Segment ------
EQUATIONS

/PAGE0 = /A8 * /A9 * /A10 * /A11 * /A12 * /A13 * /A14 * /A15

/RAM1_CE = /MREQ * /A19 * /A18 * /A17 * A16 +
           /MREQ * /A19 * /A18 * /A17 * /A16 * PAGE0

/RAM2_CE = /MREQ * /A19 * /A18 * A17

/ROM1_CE = /MREQ * /A19 * A18 * /A17 +
           /MREQ * /A19 * /A18 * /A17 * /A16 * /PAGE0

/ROM2_CE = /MREQ * /A19 * A18 * A17


;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON RAM1_CE RAM2_CE ROM1_CE ROM2_CE PAGE0

; Check all outputs inactive
SETF  /A19 /A18 /A17 /A16 /A15 MREQ /A14 /A13 /A12 /A11 /A10 /A9 A8
CHECK ROM1_CE ROM2_CE RAM1_CE RAM2_CE PAGE0

; Check page0 output active
SETF  /A19 /A18 /A17 /A16 /A15 MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK ROM1_CE ROM2_CE RAM1_CE RAM2_CE /PAGE0

; Check ROM1 enabled
SETF  /A19 /A18 /A17 /A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK /ROM1_CE ROM2_CE RAM1_CE RAM2_CE /PAGE0

; Check RAM1 enabled
SETF  /A19 /A18 /A17 /A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 A8
CHECK ROM1_CE ROM2_CE /RAM1_CE RAM2_CE PAGE0

; Check RAM1 enabled
SETF  /A19 /A18 /A17 A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK ROM1_CE ROM2_CE /RAM1_CE RAM2_CE /PAGE0

; Check RAM2 enabled
SETF  /A19 /A18 A17 /A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK ROM1_CE ROM2_CE RAM1_CE /RAM2_CE /PAGE0

; Check ROM1 enabled
SETF  /A19 A18 /A17 /A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK /ROM1_CE ROM2_CE RAM1_CE RAM2_CE /PAGE0

; Check ROM1 enabled
SETF  /A19 A18 /A17 /A16 A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK /ROM1_CE ROM2_CE RAM1_CE RAM2_CE PAGE0

; Check ROM2 enabled
SETF  /A19 A18 A17 /A16 /A15 /MREQ /A14 /A13 /A12 /A11 /A10 /A9 /A8
CHECK ROM1_CE /ROM2_CE RAM1_CE RAM2_CE /PAGE0

TRACE_OFF

;-------------------------------------------------------------------